HDL Verifier

Key Features

  • Cosimulation support for Cadence Incisive and for Mentor Graphics ModelSim and Questa
  • FPGA-in-the-loop verification using Xilinx and Altera FPGA boards
  • MATLAB functions and Simulink blocks
  • Generation of IEEE® 1666 SystemC TLM 2.0 compatible transaction-level models
  • Interactive or batch-mode cosimulation and debugging
  • Single-machine, multiple-machine, and cross-network cosimulation
Next: HDL Cosimulation Test Benches

Try HDL Verifier

Get trial software

Accelerare la progettazione di FPGA con il Simulink HDL Coder

View webinar